malt-wr
timelogic.c
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1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <string.h>
4 #include <math.h>
5 
6 #include "constype.h"
7 
9 {
10  PULSE *pclk, *psig, *tpsig;
11  int clk_cycle, sig_nr;
12  int tval, i;
13 
14  pclk=sp->sig_bgn[0];
15  clk_cycle=0;
16  while(pclk!=NULL)
17  {
18  clk_cycle++;
19  pclk=pclk->next;
20  }
21  sp->clk_cycles_nr=clk_cycle+1;
22 
23  sp->clk_times=(TIME*)calloc(sp->clk_cycles_nr, sizeof(TIME));
24  sp->sig_log= (LOGIC **)calloc(sp->signal_num, sizeof(LOGIC*));
25  for(sig_nr=1; sig_nr<sp->signal_num; sig_nr++)
26  sp->sig_log[sig_nr] = (LOGIC*)calloc(sp->clk_cycles_nr, sizeof(LOGIC));
27 
28  pclk=sp->sig_bgn[0];
29  clk_cycle=1;
30  while(pclk!=NULL)
31  {
32  sp->clk_times[clk_cycle++] = pclk->t;
33  pclk=pclk->next;
34  }
35 
36  for(sig_nr=1; sig_nr<sp->signal_num; sig_nr++)
37  {
38  psig=sp->sig_bgn[sig_nr];
39  clk_cycle=0;
40 
41  while(psig!=NULL)
42  {
43  /* find the clock cycle the pulse belongs to */
44  while(clk_cycle < sp->clk_cycles_nr-1)
45  {
46  if(sp->clk_times[clk_cycle+1] > psig->t)
47  break;
48 
49  clk_cycle++;
50  }
51 
52  /* counting the number of signal data pulses within clock cycle */
53  tpsig=psig;
54  tval = 0;
55  while(tpsig!=NULL)
56  if(sp->clk_times[clk_cycle+1] > tpsig->t)
57  { tval ++; tpsig=tpsig->next; }
58  else
59  break;
60 
61  /* assign values to
62  the array of pulse positions within clock cycle */
63  sp->sig_log[sig_nr][clk_cycle].val = tval;
64  sp->sig_log[sig_nr][clk_cycle].delta = (TIME*)calloc(tval, sizeof(TIME));
65  for(i=0; i<tval; i++, psig = psig->next)
66  sp->sig_log[sig_nr][clk_cycle].delta[i] =
67  psig->t - sp->clk_times[clk_cycle];
68 
69  if(clk_cycle >= sp->clk_cycles_nr-1)
70  break;
71 
72  }
73 
74  clk_cycle++;
75  while(clk_cycle < sp->clk_cycles_nr-1)
76  sp->sig_log[sig_nr][clk_cycle++].val=0;
77  }
78 }
79 
80 
81 
82 
83 static int same_inputs(INPUTS *ip, SIGNALS *sp, int clk_cycle)
84 {
85  int i;
86 
87  for(i=0; i<sp->ins_num; i++)
88  {
89  if(sp->sig_log[sp->clk_num + i][clk_cycle].val != ip->input_val[i])
90  return 0;
91  }
92  return 1;
93 }
94 
95 
96 static void add_input_val(INPUTS *ip, SIGNALS *sp, int clk_cycle)
97 {
98  int i;
99 
100  ip->input_val = (int*) calloc(sp->ins_num, sizeof(int));
101  for(i=0; i<sp->ins_num; i++)
102  ip->input_val[i] = sp->sig_log[sp->clk_num + i][clk_cycle].val;
103 }
104 
105 
106 static void add_delay(INPUTS *ip, int clk_cycle, TIME delta)
107 {
108  DELAYS *dp;
109 
110  dp = (DELAYS *) calloc(1, sizeof(DELAYS));
111  dp->delta = delta;
112  dp->clk_cycle=clk_cycle;
113  dp->next=NULL;
114 
115  if(ip->last_delay!=NULL)
116  ip->last_delay->next = dp;
117  else
118  ip->delay = dp;
119 
120  ip->last_delay=dp;
121 }
122 
123 
124 
126 {
127  INPUTS *ip=NULL, *last_ip=NULL, *np;
128  int k;
129 
130  for(k=1; k<sp->clk_cycles_nr; k++)
131  {
132  if(sp->sig_log[sp->signal_num-1][k].val==1)
133  {
134  np=ip;
135  while(np!=NULL)
136  {
137  if(same_inputs(np, sp, k-1))
138  {
139  add_delay(np, k-1, sp->sig_log[sp->signal_num-1][k].delta[0]);
140  goto next_cycle;
141  }
142  np=np->next;
143  }
144 
145  np=(INPUTS *)calloc(1, sizeof(INPUTS));
146  np->next=NULL;
147  if(last_ip!=NULL)
148  last_ip->next=np;
149  else
150  ip=np;
151 
152  last_ip=np;
153  add_input_val(np, sp, k-1);
154  add_delay(np, k-1, sp->sig_log[sp->signal_num-1][k].delta[0]);
155  }
156 next_cycle: ;
157  }
158  return ip;
159 }
160 
161 
162 
163 
164 int compute_holdsetup_time(SIGNALS* sp_good, SIGNALS* sp_bad,
165  HOLDSETUP *holdset, int hold1setup0)
166 {
167  int i, ival;
168  int clk_cycle;
169  TIME delta, period;
170  int done, delta_set;
171 
172  if((sp_good==NULL) || (sp_bad==NULL))
173  return 0;
174  if(sp_bad->signal_num!=sp_good->signal_num)
175  return 0;
176  if(sp_good->signal_num<3)
177  return 0;
178  if(sp_bad->clk_cycles_nr!=sp_good->clk_cycles_nr)
179  return 0;
180  if(sp_good->var_in_nr==0)
181  return 0;
182 
183  done=0;
184 
185  for(i=1; i<sp_good->clk_cycles_nr; i++)
186  {
187  if(sp_bad->sig_log[sp_bad->signal_num-1][i].val!=
188  sp_good->sig_log[sp_good->signal_num-1][i].val)
189  {
190  delta_set=1;
191  switch(hold1setup0)
192  {
193  case 1: /* HOLD TIME */
194  if(sp_good->sig_log[sp_good->var_in_nr][i-1].val>0)
195  delta=sp_good->sig_log[sp_good->var_in_nr][i-1].delta[0];
196  else
197  if(sp_good->sig_log[sp_good->var_in_nr][i-2].val>0)
198  {
199  ival = sp_good->sig_log[sp_good->var_in_nr][i-2].val;
200  delta=sp_good->sig_log[sp_good->var_in_nr][i-2].delta[ival-1];
201  period = sp_good->clk_times[i-1]-sp_good->clk_times[i-2];
202  if(delta > period/2)
203  delta = -(period-delta);
204  }
205  else
206  delta_set=0;
207  break;
208 
209  case 0: /* SETUP TIME */
210  if(sp_good->sig_log[sp_good->var_in_nr][i-1].val>0)
211  {
212  ival = sp_good->sig_log[sp_good->var_in_nr][i-1].val;
213  period=sp_good->clk_times[i]-sp_good->clk_times[i-1];
214  delta=sp_good->sig_log[sp_good->var_in_nr][i-1].delta[ival-1];
215  delta=period-delta;
216  }
217  else
218  if(sp_good->sig_log[sp_good->var_in_nr][i].val>0)
219  {
220  delta=sp_good->sig_log[sp_good->var_in_nr][i].delta[0];
221  period = sp_good->clk_times[i+1]-sp_good->clk_times[i];
222  if(delta < period/2)
223  delta = -delta;
224  else
225  delta_set=0;
226  }
227  else
228  delta_set=0;
229 
230  if(!delta_set)
231  if(sp_good->sig_log[sp_good->var_in_nr][i-2].val>0)
232  {
233  ival = sp_good->sig_log[sp_good->var_in_nr][i-2].val;
234  period=sp_good->clk_times[i-1]-sp_good->clk_times[i-2];
235  delta=sp_good->sig_log[sp_good->var_in_nr][i-2].delta[ival-1];
236  if(delta > period/2)
237  delta=period-delta;
238  else
239  delta=-delta;
240  delta_set=1;
241  }
242  }
243 
244  if(delta_set)
245  if((!done) || (delta > holdset->delta))
246  {
247  done=1;
248  holdset->delta=delta;
249  holdset->cycle=i-1;
250  holdset->input=sp_good->var_in_nr;
251  }
252  }
253  }
254 
255  return done;
256 }
TIME * clk_times
Definition: constype.h:431
struct PULSE_DESC * next
Definition: constype.h:298
TIME t
Definition: constype.h:284
int clk_cycle
Definition: constype.h:505
DELAYS * last_delay
Definition: constype.h:515
int change_into_logic(SIGNALS *sp)
Definition: timelogic.c:8
int compute_holdsetup_time(SIGNALS *sp_good, SIGNALS *sp_bad, HOLDSETUP *holdset, int hold1setup0)
Definition: timelogic.c:164
PULSE ** sig_bgn
Definition: constype.h:404
int var_in_nr
Definition: constype.h:390
int clk_cycles_nr
Definition: constype.h:434
int * input_val
Definition: constype.h:513
static int same_inputs(INPUTS *ip, SIGNALS *sp, int clk_cycle)
Definition: timelogic.c:83
int signal_num
Definition: constype.h:366
TIME * delta
Definition: constype.h:332
TIME delta
Definition: constype.h:466
DELAYS * delay
Definition: constype.h:514
int input
Definition: constype.h:472
double * delta
Definition: points.c:14
int val
Definition: constype.h:329
TIME delta
Definition: constype.h:504
int clk_num
Definition: constype.h:369
LOGIC ** sig_log
Definition: constype.h:439
static void add_input_val(INPUTS *ip, SIGNALS *sp, int clk_cycle)
Definition: timelogic.c:96
INPUTS * compute_delays(SIGNALS *sp)
Definition: timelogic.c:125
struct DELAYS_DESC * next
Definition: constype.h:506
float TIME
Definition: constype.h:54
static void add_delay(INPUTS *ip, int clk_cycle, TIME delta)
Definition: timelogic.c:106
int ins_num
Definition: constype.h:372
int cycle
Definition: constype.h:469