There are many things that can go wrong, and it is likely that something will. Most likely, the Verilog-A file contains a construct that either ADMS or the scripts can't handle. The author of ADMS describes the translator as ``alpha'', but that being said, it seems fairly complete and stable. The problem most likely resides with the XML scripts. These were adapted to WRspice using scripts for other simulators as a starting point. They will evolve to provide more complete and error-free translation. As a quick look at the script text will show, they can be hideously complex. The language itself is not well documented, though ``experts'' can figure it out from the configuration files in the ADMS installation.