The ADMS program reads the Verilog-A file, and builds a representation of the file logic in memory. A set of XML scripts access this tree and generate the C++ code to describe the device functionality. The C++ files are then compiled into a loadable module (shared library) which can be loaded into WRspice.
WRspice can load device modules in two ways. On program startup, any device modules found in the devices sub-directory in the startup directory (e.g. /usr/local/xictools/wrspice/startup/devices) will be loaded. While running, the WRspice devload command can be used to load a module, with the command argument being the path to the module. If no argument is given, a list of the modules currently loaded is printed.