The concept of tap wires may be familiar from Cadence Virtuoso. Tap wires are fully supported in Xic.
A wire is considered to be a ``tap'' of another wire if every bit in the first wire is included in the second. Note that they may have very different bit order.
If a wire is a tap for another, then the two wires are allowed to connect. Note, however, that the visual connection may serve no real purpose, as the bits are already connected by name. However, the visible indication of connectivity may make the schematic more readable. The tap wire will allow connection to a subset of the conductors in the wire being tapped.
An interesting special case is when the wire being tapped is a pure vector. In this case (only), the tap wire label need not include a name, but only a vector expression. Also in this case, a connection is required. Then, the tap wire will obtain the name from the wire being tapped.
For example, suppose that we have a net data[0:3], and we want to connect data to a scalar instance pin A. If we connect the A pin directly to the data[0:3] wire, all four bits of the wire would be connected to A, which is not what we want. Instead, create a new wire, connected to the original wire and to A. Give the new wire a label ``''. This becomes a tap wire, connecting data to A.