Via Detection

Below the check boxes mentioned above is the Via Detection group. This controls how vias are searched for and identified. As most layouts contain large numbers of vias, the algorithms used to detect vias can have a significant impact on extration time. The default settings provide the least testing and the speediest performance, however they assume that a certain layout methodology has been followed. If all vias in the layout are separate cell instances, and the via masters contain patches of the two conductors along with the via layer, then the default settings will always apply. If this is not the case, it is possible for connections to be missed, the user must understand the rest of this section.

The recognition algorithm is as follows.

1. An object on a via layer is found, usually by iterating through the spatial database over a region.

2. If the object is not a box object, and the Assume convex vias check box is checked, it is replaced temporarily by a box of half the width/height of the bounding box. This is for efficiency - the geometrical computations are much faster for box objects. In practice, a via is almost always a square, but other shapes, mostly circular approximations, are occasionally seen. In particular, in superconductive electronics we often use circular vias concentric with circular Josephson junctions. If the check box is not set, the via shape is decomposed into a trapezoid list.

3. We look for objects on the upper and lower conductor layers whose intersection intersects the assumed via shape with nonzero area. If found, a connection is indicated.

The initial ``grouping' phase establishes networks of metal objects in the cells, which contact by proximity or through vias. The next ``extraction'' phase modifies the network to account for device connections, and establishes connections to and between subcircuits. In this process, ``wire-only'' subcircuits are logically flattened into the parent cells. There are two things to keep in mind about this flattening process.

1. Only conductors are promoted into the parent cell. In particular, via material is not promoted, and must be accessed through the original cell hierarchy.

2. Consider a via cell, consisting of metal caps and a via pattern. The metal caps are connected, trivially. When the metal caps are promoted, they will tie together any contacting metal in the parent cell. Thus, we never have to recognize the via again, it has imposed its connectivity constraint and logically disappeared.

Connecting to and between subcells is a complicated and labor intensive operation. We have to iterate through all wire nets of all subcells, and test for connectivity. Connectivity can occur by direct contact, or, conceivably by a via. However, if we know that all of the vias are separate cells as described, we know that they have all been flattened away, and the hugely expensive test of looking for via connections between nets can be skipped entirely. If in the original layout a via (cell) is making the connection, in extraction the proximity test will discover the promoted, shorted via caps, and make the connection.

What if not all vias are in separate cells? In theory, the via material, and the two connected metal objects, may each occur in any subcell at any hierarchy level. In the most general case, we would need to search the entire hierarchy depth for via material, which can be painfully slow. However, other rules can apply. For example, to make a contact, one could place a square of via material on the current cell, over the metal layer intersection area of nets contained in the cell or subcells. If this method is used to connect between subcircuits, then this test must be enabled, however the search depth can remain at zero. If the via material is found in a subcell, then the search depth would have to be set appropriately.

The Via Detection group contains the following elements.

Assume convex vias
This applies when checking connectivity through a via during extraction. When set, vias that are not rectangular are assumed to be convex polygons, and connectivity testing is performed in a small rectangular region near the center of the bounding box. This is specifically for circular vias, as found in superconductive electronics. This simplifies testing and might speed extraction when circular vias are present. It should not be used if vias can take arbitrary polygonal shapes. This will have no effect on rectangular vias.

This sets/tracks the state of the ViaConvex variable.

Via search depth
If we have intersecting areas of top and bottom conductor, and we are searching for an area of via material that would connect the two metal objects, this sets the depth in the current cell hierarchy to search. The default is zero, indicating to search the current cell only. Generally, layout methodology can easily ensure that this value can be safely zero, but there may be cases that require extraction where such methodology was not practiced. In such a case, where the methodology is completely unknown, this value should be set to a large number (internally it is limited to 40, the maximum cell hierarchy depth) which will ensure that all via-induced connections are found. This can dramatically increase extraction time.

This tracks the value of the variable ViaSearchDepth, and defaults to zero if the variable is not set.

Check for via connections between subcells
By default, it is assumed that connections between subcells will be made by touching metal only. This includes the case where the metal is from a flattened wire-only cell, as would be provided by via cells as described previously. One can easily adapt layout methodology where this is true. Otherwise, this box can be checked, which will cause explicit testing for the presence of vias between subcircuit nets. This is a very expensive operation.

This tracks the whether or not the ViaCheckBtwnSubs variable is set.