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The Dump LVS Button: Test Layout vs. Schematic

The Dump LVS (Dump Layout Vs. Schematic) button in the Extract Menu compares the netlists obtained from the physical and electrical data for the hierarchy of the current cell, and lists topological and electrical differences. When the Dump LVS button is pressed, a small pop-up appears, which contains a field for setting the name of the output file, and has provision for setting the depth into the hierarchy to compare. The default name for the output file is the base name of the current cell, with a ``.lvs'' extension, and this will be written in the current directory unless a path is given to the file name. Entering 0 for the depth compares the current cell only, 1 compares the current cell and immediate subcells, and so on. The user is given a chance to view the output file upon completion.

If computed wire capacitance is included in the electrical data, the capacitors will be recognized by virtue of having a special name prefix ``C@NET''" and treated specially. Unlike other devices, there is no corresponding physical device. If found, the values will be compared with the corresponding computed net capacitance in the physical data, and an error will be reported if the two numbers differ by 1 percent or more. Wire net capacitance is considered only for the capacitors that are found in the electrical data, i.e., if they are missing no error is generated.

When the LVS data are printed out, the hierarchy of the electrical (schematic) part is used as the basis. This means that

  1. any physical structures that are not connected to the top-level cell (directly or indirectly) and are not represented in the schematic are ignored.
  2. the reverse is not true: anything in the schematic that doesn't have a physical counterpart is an error.

Thus, the schematic is favored, as anything not in the schematic and not connected physically is considered to be a ``test structure'' and is generally ignored. One of the reasons for this behavior is the potential existence of test cells and structures that might contain real devices or circuits, which aren't connected to anything but are used for process analysis. Generally, one would expect these to be ignored for LVS purposes.

However, unconnected physical subcells (cell instances) that contain extracted devices or subcircuits are explicitly checked for and listed. If the fail if unconnected physical subcells check box in the LVS panel is checked, the presence of unconnected physical subcircuits will force LVS failure of the cell. This check box tracks the state of the LvsFailNoConnect variable.



Subsections
next up previous contents index
Next: Parameterization Limitation Up: The Extract Menu: Extraction Previous: The Dump Elec Netlist   Contents   Index
Stephen R. Whiteley 2017-10-02