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The Create Via Button: Create Standard Via Variant

The Create Via button in the Edit Menu brings up the Via Creation panel, if standard vias are defined in the current technology. If no standard vias are defined, the menu entry will be grayed, and the panel will not be available. This will be the case for the example scmos and Hypres technology files provided. The xic_tech.demo technology file found with the memory chip examples does provide standard via definitions, should the user wish to try this feature.

The panel contans a number of entry areas, corresponding to the standard via parameters as described below. Of these, the numerical parameters can be changed by the user to create variants. The fields that contain layer names can not be changed, except by creating a new standard via definition. Presently, this must be done by editing the technology file.

Each row of the panel contains a description and two entry areas, as most of the entries have separate values for X and Y directions. Dimensions are in microns.

Via name, cut layer
This row contains two menus, which together provide access to all of the available standard via definitions. The menu on the right provides the process layer names that are used as ``cuts''. These are the layers that represent holes in an insulating layer, generally called ``via layers''. The menu on the left provides the names of standard vias defined which use that via layer. Most often, there is only one such definition, for a metal to metal contact. In other cases, one of the ``conductors'' may be an implanted area, in which case there may be several choices. When the user selects a standard via using these menus, the other fields in the panel will be set to the default values for the various parameters.

Layer 1, Layer 2
These are the layer names of the two layers to be connected by the via. These can not be changed by the user, except by selecting another standard via. In Xic, Layer 1, and the `1' designation in general, corresponds to the bottom conductor.

Cut width, height
The ``cut'' is the feature on the via layer that actually forms the contact. In a standard via, this is always rectangular. In a semiconductor process, this is almost always a square of a fixed size. Although the two dimensions can be changed by the user, one must be aware of the relevant design rules before doing so.

Cut rows, columns
In order to lower contact resistance and handle higher current, the cut structure can be arrayed. In some situations it may be possible to simply increase the size of a single cut, but in more advanced processing the cut size is fixed and arrays are used. This is probably the most common variant.

Cut spacing X,Y
This is the space between cut edges (not center-to-center) in the X and Y directions. This is only useful if the cut is arrayed. In general, the two values are the same, and fixed at a minimum from a design rule. The values should be changed only with knowledge of the appropriate design rules.

Enclosure 1 X,Y
In addition to the cut, the via will also contain squares of the two metal layers. The ``Enclosure'' is the distance the metal layer overhangs the cut. The two numbers apply to the bottom layer, in the X and Y directions. The two numbers are typically set to a design rule minimum, and should be changed only with knowledge of the design rules involved.

Offset 1 X,Y
If the offset parameters are zero, the metal rectangle is centered on the cut. One can set the offset to a nonzero value, which will move the center of the metal rectangle relative to the center of the cut. This entry applies to the bottom conductor. These entries are almost always zero.

Enclosure 2 X,Y
As for Enclosure 1, but the values apply to the top conductor.

Offset 2 X,Y
As for Offset 1, but the values apply to the top conductor.

Origin offset X,Y
This is the origin of the sub-master coordinate system, which if zero is centered on the cut array. This is the same as Virtuoso, but appears to differ from the OpenAccess specification which seems to indicate that the origin is centered on the lower-left cut element. All features of the via are drawn relative to this offset, so there are no design rule implications. These values are most often zero.

Implant 1, Implant 2
Up to two additional rectangles can be drawn in the via, representing implant areas. These may apply when contacting activated substrate areas, where additional spacing rules to an implant region edge may apply. If defined in the standard via definition, one or both of these entries may contain an implant layer name. If not, the entry area is grayed. The layer names can not be changed by the user, except by selecting another standard via.

Implant 1 enc X,Y
If an Implant 1 layer is present, these entries will contain the enclosure values of the implant 1 layer rectangle relative to the bottom conductor rectangle. That is, the implant 1 rectangle will overhang the bottom conductor rectangle in the X and Y directions by the values given.

Implant 2 enc X,Y
If an Implant 2 layer is present, these entries will contain the enclosure values of the implant 2 layer rectangle relative to the top conductor rectangle. That is, the implant 2 rectangle will overhang the top conductor rectangle in the X and Y directions by the values given.

The easiest way to understand the effect of these parameters is to create some vias.

Entering the parameters has no effect until the Apply button is pressed. When Apply is pressed, a new internal sub-master cell for the variant is created if necessary, and the via structure is ghost-drawn and attached to the mouse pointer. Instances of the via will be placed where the user clicks in a drawing window. As for normal subcells, the current transform will be applied to the via. Most process rules will not accept 45-degree rotations. The placement mode can be exited by pressing the Esc key.


next up previous contents index
Next: The Flatten Button: Flatten Up: The Edit Menu: Edit Previous: The Create Cell Button:   Contents   Index
Stephen R. Whiteley 2017-04-09