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.adc Line

General Form:
.adc
This line of WRspice input converts a SPICE signal into a digital signal for the Verilog block. Such lines are used only as an adjunct to Verilog.

General Form:
.adc digital_var node_name [offset] [delta]

The parameters have the following interpretation:

digital_var
Qualified name of a variable in the Verilog block, can include a range specification.
node_name
Node of circuit to convert, not including any ``v()"''. Current branches can be accessed as ``name#branch''.
offset (optional, default 0)
Real number subtracted from value before conversion.
delta (optional, default 1)
The size of an lsb for conversion.

The transfer function is:

value = value - offset
if (value > 0)
value = value + 0.5*delta
else
value = value - 0.5*delta
conversion = (integer) (value/delta)

The offset and delta arguments to the .adc line can be expressions. These will be evaluated once only, as the circuit is read in.


next up previous contents index
Next: Voltage and Current Sources Up: Verilog Interface Previous: .verilog, .endv Lines   Contents   Index
Stephen R. Whiteley 2006-10-23