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Index
- 1
- A. Vladimirescu and S. Liu, The Simulation of MOS
Integrated Circuits Using SPICE2, ERL Memo No. ERL M80/7, Electronics
Research Laboratory, University of California, Berkeley, Oct. 1980.
- 2
- B. J. Sheu, D. L. Scharfetter, and P. K. Ko,
SPICE2 Implementation of BSIM, ERL Memo No. ERL M85/42, Electronics
Research Laboratory, University of California, Berkeley, May 1985.
- 3
- J. R. Pierret, A MOS Parameter Extraction Program
for the BSIM Model, ERL Memo Nos. ERL M84/99 and M84/100, Electronics
Research Laboratory, University of California, Berkeley, Nov. 1984.
- 4
- Min-Chie Jeng, Design and Modeling of Deep-Submicrometer
MOSFETs, ERL Memo Nos. ERL M84/99 and ERL M90/90, Electronics
Research Laboratory, University of California, Berkeley, October 1990.
- 5
- Soyeon Park, Analysis and SPICE implementation of High
Temperature Effects on MOSFET, Master's Thesis, University of California,
Berkeley, December 1986.
- 6
- Clement Szeto, Simulator of Temperature effects in
MOSFETs (STEIM), Master's Thesis, University of California, Berkeley,
May 1988.
- 7
- A. E. Parker and D. J. Skellern, An Improved FET Model
for Computer Simulators, IEEE Trans. CAD, vol. 9, no.5, pp. 551-553,
May 1990.
- 8
- Y. Cheng, M. Chan, K. Hui, M-C Jeng, Z. Liu, J. Huang,
K. Chen, J. Chen, R. Tu, P. Ko and C. Hu, BSIM3v3 Manual,
Department of Electrical Engineering and Computer Sciences,
University of California, Berkeley, 1996.
- 9
- R. Saleh and A. Yang, Editors, Simulation and Modeling,
IEEE Circuits and Devices, vol. 8, no. 3, pp. 7-8 and 49, May 1992.
- 10
- H. Statz et al., GaAs FET Device and Circuit
Simulation in SPICE, IEEE Transactions on Electron Devices, Vol. 34,
Number 2, February 1987 pp. 160-169.
- 11
- R. E. Jewett, Josephson Junctions in SPICE2G5,
ERL Memo, Electronics Research Laboratory, University of California,
Berkeley, 1982.
- 12
- S. R. Whiteley, Josephson Junctions in SPICE3,
IEEE Trans. Magn., vol. 27, no. 2, pp. 2902-2905, March 1991.
- 13
- J. S. Roychowdhury and D. O. Pederson, Efficient
Transient Simulation of Lossy Interconnect, Proc. DAC 91.
- 14
- Shen Lin and Ernest S. Kuh, Transient Simulation of Lossy
Interconnect, Proc. DAC, pp 81-86, 1992.
Stephen R. Whiteley
2012-09-24