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Creating Loadable Modules from Veriolog-A

WRspice provides support for building loadable modules from Verilog-A model source. Many new compact device models have been released in this format, as it is (theoretically) portable to all simulators. Most commercial simulators now have this capability.

To build modules from Verilog-A source, the Whiteley Research version of the open-source adms-2.3.x package must be installed on the system. This is included in the XicTools packages and source. The XicTools version of adms contains the latest enhancements and bug fixes for use with WRspice, and should be used in preference to other versions of this software.

The devkit/README file provides instructions on how to build a module, and there are several examples. Pre-built modules are provided. These can be loaded into WRspice and used.


Stephen R. Whiteley 2022-09-18